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40- channel, 3 v/5 v, single - supply, 12- bit, dense dac ? data sheet ad5381 features guaranteed m onotonic inl e rror: 1 lsb max on -c hip 1.25 v /2.5 v, 10 ppm/ c r eference temperature r ange: C40 c to +85 c rail - to -r ail o utput a mplifier p ower - down package t ype: 100 - lead lqfp (14 mm 14 mm) user i nterfaces: parallel serial (spi ?-/ qsp i?- /microwire ?-/ dsp - compatible , featuring d ata r eadback) i 2 c?-c ompatible robust 6.5 kv hbm and 2 kv ficdm esd rating integrated functions channel m onitor simultaneous o utput u pdate via ldac clear f unction to u ser -p rogrammable c ode ampli fier b oost m ode to o ptimize s lew r ate user -p rogrammable o ffset and g ain a djust toggle m ode e nables s quare wave g eneration thermal m onitor s applications variable o ptical a ttenuators (v oas) level s etting (ate) optical m icro - electro - mechanical s ystems (mems) control s ystems instrumentation functional block diagram r r vout0 dac 0 dac reg0 input reg0 12 12 12 12 12 12 m reg0 c reg0 1.25v/2.5v reference power-on reset 39- to-1 mux vout1 vout2 vout3 vout4 vout5 dac 1 dac reg1 input reg1 12 12 12 12 12 12 m reg1 c reg1 vout6 dac 6 dac reg6 input reg6 12 12 12 12 12 12 m reg6 c reg6 vout7 vout8 dac 7 dac reg7 input reg7 12 12 12 12 12 12 m reg7 c reg7 5 03732-001 fifo + sta te machine + contro l logic inter f ace contro l logic db 1 1/(din/sda) db10/(sclk/scl) db9/(spi/i 2 c) db8 a5 a0 vout0???vout38 reg0 reg1 reset bus y clr pd ser/p ar fifo en cs/(sync/ad0) wr/(dcen/ad1) sdo vout39/mon_out ldac vout38 dvdd (3) dgnd (3) a vdd (5) agnd (5) dac_gnd (5) refgnd refout/refin signal_gnd (5) ad5381 db0 r r r r r r figure 1. rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibil i ty is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specification s subject to change without notice. no license is granted by implication or otherwise under any patent o r patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9 10 6, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2004 C 2012 analog devices, inc. all rights reserved.
ad5381 data sheet rev. d | page 2 of 40 table of contents general description ......................................................................... 3 ? specifications ..................................................................................... 4 ? ad5381-5 specifications ............................................................. 4 ? ad5381-3 specifications ............................................................. 6 ? ac characteristics ........................................................................ 7 ? timing characteristics ..................................................................... 8 ? serial interface timing ................................................................ 8 ? i 2 c serial interface timing ........................................................ 10 ? parallel interface timing ........................................................... 11 ? absolute maximum ratings .......................................................... 13 ? esd caution ................................................................................ 13 ? pin configuration and function descriptions ........................... 14 ? terminology .................................................................................... 17 ? typical performance characteristics ........................................... 18 ? functional description .................................................................. 21 ? dac architecturegeneral ..................................................... 21 ? data decoding ............................................................................ 21 ? on-chip special function registers (sfr) ............................ 22 ? sfr commands .......................................................................... 22 ? hardware functions ....................................................................... 25 ? reset function ............................................................................ 25 ? asynchronous clear function .................................................. 25 ? busy and ldac functions...................................................... 25 ? fifo operation in parallel mode ............................................ 25 ? power-on reset .......................................................................... 25 ? power-down ............................................................................... 25 ? interfaces.......................................................................................... 26 ? dsp-, spi-, microwire-compatible serial interfaces ..... 26 ? i 2 c serial interface ..................................................................... 28 ? parallel interface ......................................................................... 30 ? microprocessor interfacing ....................................................... 31 ? application information ................................................................ 33 ? power supply decoupling ......................................................... 33 ? typical configuration circuit .................................................. 33 ? monitor function ....................................................................... 34 ? toggle mode function ............................................................... 34 ? thermal monitor function ....................................................... 34 ? optical attenuators .................................................................... 35 ? utilizing fifo ............................................................................. 35 ? outline dimensions ....................................................................... 37 ? ordering guide .......................................................................... 37 ? revision history 9 /12rev. c to rev. d changes to product title .................................................................. 1 changes to general description section and table 1 .................. 3 deleted table 2; renumbered sequentially ................................... 3 5/12rev. b to rev. c changes to features .......................................................................... 1 changes to table 3 ............................................................................ 4 changes to table 4 ............................................................................ 6 changes to output voltage settling time and slew rate parameters, table 5 ........................................................................... 7 changes to t 14 , t 17 , and t 19 parameters, table 6 .............................. 8 changes to table 9 .......................................................................... 13 changes to figure 10, figure 11, and figure 14 ......................... 18 changes to figure 16 to figure 18 and figure 20 ....................... 19 updated outline dimensions and changes to ordering guide .... 37 8/05rev. a to rev. b changes to table 2 ............................................................................. 3 changes to specifications section ................................................... 4 changes to absolute maximum ratings section ....................... 13 changes to figure 43 ...................................................................... 35 changes to ordering guide .......................................................... 37 6/04data sheet changed from rev. 0 to rev. a changes to ordering guide ........................................................... 36 5/04revision 0: initial version
data sheet ad5381 rev. d | page 3 of 40 general description the ad5381 is a complete, single - supply, 40 - channel, 12 - bit dense d ac ? available in a 100 - lead lqfp package. all 40 c hannels have an on - chip output amplifier with rail - to - rail operation. the ad5381 includes a programmable internal 1.25 v/2.5 v, 10 ppm/c reference, an on - chip channel monitor function that multiplexes the analog outputs to a common mon_o u t pin for externa l monitoring , and an output amplifier boost mode , which allows optimization of the amplifier slew rate. the ad5381 contains a double - buffered parallel interface featur ing 20 ns wr pulse width, an spi - /qspi - /microwire - /dsp - compatible seria l interface with interfa ce speeds in excess of 30 mhz , and an i 2 c- compatible interface that supports a 400 khz data transfer rate. an input register followed by a dac register provides double buffering, allowing the dac outputs to be updated independ - entl y or simultaneously using the ldac input. each channel has a programmable gain and offset adjust register that allows the user to fully calibrate any dac chan - nel. power consumption is typically 0. 25 ma/channel with boost mode disabled . table 1 . other low voltage single - supply dacs in product family model resolution avdd range output channels linearity error (lsb) package description package option ad5380bst z-5 14 bits 4.5 v to 5.5 v 40 4 100- lead lqf p st - 100 ad5380bst z-3 14 bits 2.7 v to 3.6 v 40 4 100- lead lqfp st - 100 ad5382bst z-5 14 bits 4.5 v to 5.5 v 32 4 100- lead lqfp st - 100 ad5382bst z-3 14 bits 2.7 v to 3.6 v 32 4 100- lead lqfp st - 100 ad5383bst z-5 12 bits 4.5 v to 5.5 v 32 1 100- lead lqfp st - 100 ad5383bst z-3 12 bits 2.7 v to 3.6 v 32 1 100- lead lqfp st - 100 ad5390bst z-5 14 bits 4.5 v to 5.5 v 16 3 52- lead lqfp st - 52 ad5390bcp z-5 14 bits 4.5 v to 5.5 v 16 3 64- lead lfcsp cp - 64 ad5390bst z-3 14 bi ts 2.7 v to 3.6 v 16 4 52- lead lqfp st - 52 ad5390bcp z-3 14 bits 2.7 v to 3.6 v 16 4 64- lead lfcsp cp - 64 ad5391bst z-5 12 bits 4.5 v to 5.5 v 16 1 52- lead lqfp st - 52 ad5391bcp z-5 12 bits 4.5 v to 5.5 v 16 1 64- lead lfcsp cp - 64 ad 5391bst z-3 12 bits 2.7 v to 3.6 v 16 1 52- lead lqfp st - 52 ad5391bcp z-3 12 bits 2.7 v to 3.6 v 16 1 64- lead lfcsp cp - 64 ad5392bst z-5 14 bits 4.5 v to 5.5 v 8 3 52- lead lqfp st - 52 ad5392bcp z - 5 14 bits 4.5 v to 5.5 v 8 3 64 - lead lfc sp cp - 64 ad5392bst z - 3 14 bits 2.7 v to 3.6 v 8 4 52 - lead lqfp st - 52 ad5392bcp z-3 14 bits 2.7 v to 3.6 v 8 4 64- lead lfcsp cp - 64
ad5381 data sheet rev. d | page 4 of 40 specifications ad5381 - 5 specifications avd d = 4.5 v to 5.5 v; dvdd = 2.7 v to 5.5 v, agnd = dgnd = 0 v; e xt ernal refin = 2.5 v; all specifications t min to t max , unless otherwise noted . table 2 . parameter ad5381 -5 1 unit test conditions/comments accuracy output u nloaded resolution 12 bits relative accuracy 2 (inl) 1 lsb max d ifferential nonlinearity (dnl) 1 lsb max guaranteed monotonic over temperature zero - scale error 4 mv max offset error 4 mv max measured at c ode 8 in the linear region offset error tc 5 v/c typ gain error 0.0 5 % fsr max at 25c 0.06 % fsr max t min to t max gain temperature coefficient 3 2 ppm fsr/c typ dc crosstalk 3 1 lsb max reference input/output reference input 3 reference input voltage 2.5 v 1% for speci fied performance, avdd = 2 refin + 50 mv dc input impedance 1 m ? min typically 100 m? input current 10 a max typically 30 na reference range 1 to avdd /2 v min/max reference output 4 enabled via cr8 in the ad5381 c ontrol r egister , cr10 selec ts the reference voltage output voltage 2.495/2.505 v min/max at ambient , o ptimized for 2.5 v operation. cr10 = 1 1.22/1.28 v min/max cr10 = 0 reference tc 10 p pm /c max temperature range: +25 c to +85c 15 ppm/c max temperature range: ?40 c to +85c output impedance 800 ? typ output characteristics 3 output voltage range 2 0/ avdd v min/max short - circuit current 40 ma max load current 1 ma max capacitive load stabilit y r l = 200 pf max r l = 5 k ? 1000 pf max dc output impedance 0.6 ? max monitor pin output impedance 1 k ? typ three - state leakage current 100 na typ logic inputs (except sda/scl) 3 dvdd = 2.7 v to 5.5 v v ih , input high voltage 2 v min v il , input low voltage dvdd > 3.6 v 0.8 v max dvdd 3.6 v 0.6 v max input current 10 a max total for all pins ; t a = t min to t max pin capacitance 10 pf max
data sheet ad5381 rev. d | page 5 of 40 parameter ad5381 -5 1 unit test conditions/comments logic inputs (sda, scl onl y) 3 v ih , input high voltage 0.7 dvdd v min smbus compatible at dvdd < 3.6 v v il , input low voltage 0.3 dvdd v max smbus compatible at dvdd < 3.6 v i in , input leakage current 1 a max v h yst , input hyster esis 0.05 dvdd v min c in , input capacitance 8 pf typ glitch rejection 50 ns max input filtering suppresses noise spikes of less than 50 ns logic outputs ( busy , sdo) 3 v ol , output low voltage 0.4 v max dvdd = 5 v 10%, sinking 200 a v oh , output high voltage dvdd C 1 v min dvdd = 5 v 10%, sourcing 200 a v ol , output low voltage 0.4 v max dvdd = 2.7 v to 3.6 v, sinking 200 a v oh , output high voltage dvdd C 0.5 v min dvdd = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 3 v ol , output low voltage 0.4 v max i si n k = 3 ma 0.6 v max i si n k = 6 ma three - state leakage current 1 a max three - state output capacitance 8 pf typ power requirements avdd 4.5/5.5 v min/max dvdd 2.7/5.5 v min/max power supply sensitivity 3 ? mid s cale/ ? v dd C 85 db typ ai dd 0. 37 5 ma/ c hannel max outputs unloaded, b oost off ; 0 .2 5 ma/channel typ 0. 4 75 ma/ c hannel max outputs unloaded, b oost on. ; 0.32 5 ma /channel typ di dd 1 ma max v ih = dvdd , v il = dgnd ai dd (power - down) 20 a max typically 100 na di dd (power - down) 20 a max typically 1 a power dissipation 80 mw max outputs unloaded, b oost off, avdd = dvdd = 5 v 1 ad5381 - 5 is calibrated using an exter nal 2.5 v reference. temperature range for a ll v ersions: C 40c to +85c . 2 accuracy guar anteed from vout = 10 mv to avdd C 50 mv . 3 guaranteed by characterization, not production tested. 4 default on the ad5381 - 5 is 2.5 v. programmable to 1.25 v via cr10 in the ad5381 control register; operating the ad5381 - 5 with a 1.25 v reference will lead to degraded accuracy specifications.
ad5381 data sheet rev. d | page 6 of 40 ad5381 -3 specifications avd d = 2.7 v to 3.6 v; dvdd = 2.7 v to 5.5 v, agnd = dgnd = 0 v; e xternal refin = 1.25 v; all specifications t mi n to t max , unless otherwise noted . table 3 . parameter ad5381 -3 1 unit test conditions/comments accuracy output u nloaded resolution 12 bits relative accuracy 2 (inl) 1 lsb max differential nonlinearity (dnl) 1 lsb ma x guaranteed monotonic over temperature zero - scale error 4 mv max offset error 4 mv max measured at c ode 16 in the linear region offset error tc 5 v/c typ gain error 0.0 5 % fsr max at 25 c 0. 1 % fsr max t min to t max gain temperatur e coefficient 3 2 ppm fsr/c typ dc crosstalk 3 1 lsb max reference input/output reference input 3 reference input voltage 1.25 v 1% for specified performance dc input impedance 1 m? min typically 100 m? input current 10 a max typically 30 na reference range 1 to avdd /2 v min/max reference output 4 enabled via cr8 in the ad5381 c ontrol r egister cr10 selects the reference voltage. output voltage 1.24 5 /1.25 5 v min/max at ambient ; o ptimized for 1.25 v operation ; cr10 = 0 2.4 7 /2.5 3 v min/max cr10 = 1 reference tc 10 ppm /c max temperature range: +25 c to +85c 15 ppm / c max temperature range: C 40c to +85c output impedance 800 ? typ output characteristics 3 output voltage range 2 0/ avdd v min/max short - circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l = 5 k? 1000 pf max dc output impedance 0.6 ? max monitor pin output impedance 1 k ? typ three - state leakage current 100 na typ logic inputs (except sda/scl) 3 dvdd = 2.7 v to 3.6 v v ih , input high voltage 2 v min v il, input low voltage dvdd > 3.6 0.8 v max dvdd 3.6 0.6 v max input current 1 a max total for all pins; t a = t min to t max pin capacitance 10 pf max logic inputs (sda, scl only) 3 v i h , input high voltage 0.7 dvdd v min smbus compatible at dvdd < 3.6 v v il , input low voltage 0.3 dvdd v max smbus compatible at dvdd < 3.6 v i in , input leakage current 1 a max v h yst , input hysteresis 0.05 dvdd v min c in , input capacitance 8 pf typ glitch rejection 50 ns max input filtering suppresses noise spikes of less than 50 ns
data sheet ad5381 rev. d | page 7 of 40 parameter ad5381 -3 1 unit test conditions/comments logic outputs ( busy , sdo) 3 v ol , output low voltage 0.4 v max sinking 200 a v oh , outp ut high voltage dvdd C 0.5 v min sourcing 200 a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 3 v ol , output low voltage 0.4 v max i si n k = 3 ma 0.6 v max i si n k = 6 ma three - state leakage current 1 a max three - state output capacitance 8 pf typ power requirements avdd 2.7/3.6 v min/max dvdd 2.7/5.5 v min/max power supply sensitivity 3 ? midscale/ ? v dd C 85 db typ ai dd 0.375 ma/ c hannel max o utputs unloaded, b oost off ; 0.2 5 ma/channel typ 0. 4 75 ma/ c hannel max outputs unloaded, boost on; 0. 32 5 ma/channel typ di dd 1 ma max v ih = dvdd , v il = dgnd a i dd (power - down) 2 0 a max typically 100 na di dd (power - down) 20 a max typically 1 a power dissipation 48 mw max outputs unloaded, b oost off, avdd = dvdd = 3 v 1 ad5381 - 3 is calibrated using an external 1.25 v reference. temperature range is C 40c to +85c. 2 accuracy guaranteed from vout = 10 mv to avdd C 50 mv. 3 guaranteed by characterization, not production tested. 4 d efault on the ad 5381- 3 is 1.25 v . programmable to 2.5 v via cr10 in the ad 5381 control register; operating the ad 5381- 3 with a 2.5 v reference will lead to degraded accura cy specifications and limited input code range. ac characteristics 1 avd d = 4.5 v to 5.5 v or 2.7 v to 3.6 v ; dvdd = 2 .7 v to 5.5 v; agn d = dgnd = 0 v. table 4 . parameter all unit test conditions/comments dynamic performance output voltage settling time 1/4 scale to 3/4 scale change settling to 1 lsb 3 s typ 8 s max slew rate 2 1.5 v/s typ boost mode off, cr9 = 0 2.5 v/s typ boost mode on, cr9 = 1 digital - to - analog glitch energy 12 nv - s typ glitch impulse peak amplitude 15 mv typ dac - to - dac crosstalk 1 nv - s typ see terminology section digi tal crosstalk 0.8 nv - s typ digital feedthrough 0.1 nv - s typ effect of input bus activity on dac output under test output noise 0.1 hz to 10 hz 15 v p - p typ external r eference, m idscale loaded to dac 40 v p - p typ internal r eference, m idscale loaded to dac output noise spectral density @ 1 khz 150 nv/hz typ @ 10 khz 100 nv/hz typ 1 guaranteed by design and characterization, not production tested. 2 slew rate can be programmed via the current boost control bit in the ad5381 control register.
ad5381 data sheet rev. d | page 8 of 40 timing characteristi cs serial interface timing dvdd = 2.7 v to 5.5 v; avd d = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted. table 5 . parameter 1 , 2 , 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 4 13 ns min 24 th sclk falling edge to sync falling edge t 6 4 33 ns min minimum sync low time t 7 10 ns min minimum sync high time t 7a 50 ns min minimum sync high time in readback mode t 8 5 ns min data setup time t 9 4.5 ns min data hold time t 10 4 30 ns max 24 th sclk falling edge to bus y falling edge t 11 670 ns max busy pulse width low (single channel update) t 12 4 20 ns min 24th sclk falling edge to ldac falling edge t 13 20 ns min ldac puls e width low t 14 2 s max busy rising edge to dac output response time t 15 0 ns min busy rising edge to ldac falling edge t 16 100 ns min ldac falling edge to dac output response time t 17 3 s typ dac output settling time t 18 20 ns min clr pulse width low t 19 40 s max clr pulse activation time t 20 5 20 ns max sclk rising edge to sdo valid t 21 5 5 ns min sclk falling edge to sync rising edge t 22 5 8 ns min sync rising edge to sclk rising edge t 23 20 ns min sync rising edge to ldac falling edge 1 guaranteed by design and characterization , not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of v cc ) and are timed from a voltage level of 1.2 v. 3 see figure 2 , figure 3 , figure 4 , a nd figure 5 . 4 standalone mode only. 5 daisy - chain mode only. c l 50pf to output pin v oh (min) or v ol (max) 200a 200a i ol i oh 03732-002 figure 2 . load circuit for digital output timing
data sheet ad5381 rev. d | page 9 of 40 1 ldac active during busy. 2 ldac active after busy. busy sync ldac 1 ldac 2 clr vout vout2 vout1 din sclk 03732-003 t 7 t 8 t 9 t 4 t 3 t 1 t 2 t 5 t 17 t 17 t 12 t 13 t 18 t 19 t 16 t 14 t 10 t 15 t 13 t 11 t 6 db0 db23 24 24 figure 3 . serial interface timing diagram (stand a lone m ode) t 7a 24 48 sclk sync din sdo db23 db0 db23 db0 db23 db0 input word specifies register to be read undefined nop condition selected register data clocked out 03732-004 figure 4 . serial interface timing diagram ( data readback mode ) t 22 t 13 t 23 t 21 t 2 t 3 t 20 t 8 t 9 t 7 t 4 t 1 sclk sync sdo din ldac 48 24 db23 db0 db0 db23 db23 db0 input word for dac n input word for dac n + 1 undefined input word for dac n 03732-005 figure 5 . serial interface timing diagram (daisy - chain m ode)
ad5381 data sheet rev. d | page 10 of 40 i 2 c serial interface timing dvdd = 2.7 v to 5.5 v; avd d = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted . table 6 . parameter 1 , 2 limit at t min , t max unit description f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t h d ,sta , start/repeated start condition hold time t 5 100 ns min t su ,d at , data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t hd,dat , data hold time t 7 0.6 s min t su ,sta , setup time for repeated start t 8 0.6 s min t su ,sto , st op condition setup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 300 ns m ax t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0. 1 c b 4 ns min t f , fall time of scl and sda when transmitting c b 400 pf ma x capacitive load for each bus line 1 guaranteed by design and characterization, not production tested. 2 see figure 6 . 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of scls falling edge. 4 c b is the total capacitance, in pf, of one bus li ne. t r and t f are measu red between 0.3 dvdd and 0.7 dvdd. start condition repeated start condition stop condition t 9 t 3 t 1 t 11 t 4 t 10 t 4 t 5 t 7 t 6 t 8 t 2 sda scl 03732-006 figure 6 . i 2 c- compatible serial interface timing diagram
data sheet ad5381 rev. d | page 11 of 40 parallel interface timing dvdd = 2.7 v to 5.5 v; avd d = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t m in to t max , unless otherwise noted . table 7 . parameter 1 , 2 , 3 limit at t min , t max unit description t 0 4.5 ns min reg0, reg1, address to wr rising edge setup time t 1 4.5 ns min reg0, reg1, address to wr rising edge hold time t 2 20 ns min cs pulse width low t 3 20 ns min wr pulse width low t 4 0 ns min cs to wr falling edge setup time t 5 0 ns min wr to cs rising edge hold time t 6 4.5 ns min data to wr rising edge setup time t 7 4.5 ns min data to wr rising edge hold time t 8 20 ns min wr pulse width hig h t 9 4 700 ns min minimum wr cycle time (single - channel write) t 10 4 30 ns max wr rising edge to busy falling edge t 11 4 , 5 670 ns max busy pulse width low (single - channel update) t 12 30 ns min wr rising edge to ldac falling edge t 13 20 ns min ldac pulse width low t 14 100 ns max bu sy rising edge to dac output response time t 15 20 ns min ldac rising edge to wr rising edge t 16 0 ns min busy rising edge to ldac falling edge t 17 100 ns min ldac falling edge to dac output response time t 18 8 s typ dac output settling time, boost mode off t 19 20 ns min clr pulse width low t 20 12 smax clr pulse activation time 1 guaranteed by d esign and characterization, not production tested. 2 all input signals are specified with t r = t r = 5 ns (10% to 90% of dvdd) and timed from a voltage level of 1.2 v. 3 see figure 7 . 4 see figure 29 . 5 meas ured with the load circuit of figure 2 .
ad5381 data sheet rev. d | page 12 of 40 t 18 t 18 t 19 t 20 t 13 t 3 t 2 t 8 t 13 t 11 t 9 t 12 t 0 t 1 t 15 t 7 t 6 t 17 t 16 t 10 t 14 t 4 t 5 reg0, reg1, a5...a0 cs wr db11...db0 busy ldac 1 vout1 vout2 clr vout ldac 2 1 ldac active during busy. 2 ldac active after busy. 03732-007 figure 7 . parallel interface timing diagram
data sheet ad5381 rev. d | page 13 of 40 absolute maximum rat ings t a = 25c, unless otherwise noted . 1 table 8 . parameter rating avdd to agnd C 0.3 v to +7 v dvdd to dgnd C 0.3 v to +7 v digital inputs to dgnd C 0.3 v t o dvdd + 0.3 v sda/scl to dgnd C 0.3 v to +7 v digital outputs to dgnd C 0.3 v to dvdd + 0.3 v refin/refout to agnd C 0.3 v to avdd + 0.3 v agnd to dgnd C 0.3 v to +0.3 v voutx to agnd C 0.3 v to avdd + 0.3 v analog inputs to agnd C 0.3 v to avdd + 0.3 v operating temperature range commercial (b version) C 40c to +85c storage temperature range C 65c to +150c junctiontemperature (t j max ) 150c 100 -l ead lqfp package ja thermal impedance 44c/w reflow soldering peak temperature 230c reflow soldering (pb - free) peak temperature 260(0/ - 5) c time at peak temperature 10 s ec to 40 s ec esd hbm 6.5 kv ficdm 2 kv 1 transient currents of up to 100 ma will not cause scr latch - up . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute ma xi - mum rating conditions for extended periods may affect device reliability. esd c aution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge w ithout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradati on or loss of functionality.
ad5381 data sheet rev. d | page 14 of 40 pin configuration and function descripti ons reset db5 db4 db3 db2 db1 db0 nc nc reg0 reg1 vout23 vout22 vout21 vout20 avdd3 agnd3 dac_gnd3 signal_gnd3 vout19 vout18 vout17 vout16 avdd2 agnd2 59 74 75 69 70 71 72 67 68 66 73 64 65 60 61 62 63 57 58 55 56 53 5 4 52 51 signal_gnd5 dac_gnd5 agnd5 avdd5 vout5 vout6 vout7 vout32 vout33 vout34 vout35 vout36 vout37 vout38 vout39/mon_out vout8 vout9 vout10 vout11 vout12 dac_gnd2 signal_gnd2 vout13 vout14 vout15 26 28 27 29 30 32 33 34 35 36 31 37 38 39 40 42 43 44 45 41 46 47 48 49 50 cs/(sync/ad0) db11/(din/sda) db10/(sclk/scl) db9/(spi/i 2 c) db8 db7 db6 sdo/(a/b) dvdd dgnd dgnd a5 a4 a3 a2 a1 a0 dvdd dvdd dgnd ser/par pd wr (dcen/ad1) ldac busy 100 98 99 97 96 95 94 92 91 90 89 88 87 93 86 85 84 82 81 80 79 78 77 76 83 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 24 25 fifo en clr vout24 vout25 vout26 vout27 signal_gnd4 dac_gnd4 agnd4 avdd4 vout28 vout29 vout30 vout31 refgnd refout/refin signal_gnd1 dac_gnd1 avdd1 vout0 vout1 vout2 vout3 vout4 agnd1 pin 1 identifier ad5381 top view (not to scale) 03732-008 nc = no connect figure 8 . 100- lead lqfp pin configuration table 9 . pin function descriptions mnemonic function voutx buffered analog outputs for channel x. each analog output is driven by a rail - to - rail output amplifier operating at a gain of 2. each output is capable of driving an output load of 5 k? to ground. typical output impedance is 0.5 ?. signal_gnd(1 C 5) analog ground reference point s for each group of eight output channels. all signal_gnd pins are tied together internally and should be connected to the agnd plane as close as possible to the ad5381. dac_gnd(1 C 5) each group of eight channels contains a dac_gnd pin. this is the groun d reference point for the internal 12 - bit dac. these pins shound be connected to the agnd plane. agnd(1 C 5) analog ground reference point. each group of eight channels contains an agnd pin. all agnd pins should be connected externally to the agnd plane. avdd(1 C 5) analog supply pins. each group of eight channels has a separate avdd pin. these pins are shorted internally and should be decoupled with a 0.1 f ceramic capacitor and 10 f tantalum capacitor . operating range for the ad5381 - 5 is 4.5 v to 5.5 v; operating range for the ad5381 - 3 is 2.7 v to 3.6 v. dgnd ground for all digital circuitry. dvdd logic power supply. guaranteed operating range is 2.7 v to 5.5 v. it is recommended that these pins be decoupled with a 0.1 f ceramic and a 10 f tanta lum capacitors to dgnd. ref gnd ground reference point for the internal reference.
data sheet ad5381 rev. d | page 15 of 40 mnemonic function refout/refin the ad5381 contains a common refout/refin pin. when the internal reference is selected, this pin is the reference output. if the application requires an external reference, it can be applied to this pin and the internal reference can be disabled via the control register. the default for this pin is a reference input. vout39/mon_out this pin has a dual function. it acts a s a buffered output for c hannel 39 in d efault mode. however, when the monitor function is enabled, this pin acts as the output of a 39 - to - 1 channel multiplexer that can be programmed to multiplex one of c hannels 0 to 38 to the mon_out pin. the mon_out pins output impedance is typically 500 ? a nd is intended to drive a high input impedance like that exhibited by sar adc inputs. ser/ par interface select input. this pin allows the user to select whether the serial or parallel interface is used. if it is tied high, the serial interface mode is selected and pin 97 ( spi /i 2 c ) is used to determine if the interface mode is spi or i 2 c . parallel interface mode is selected when ser/ par is low. cs /( sync /ad0) in para llel interface mode, this pin acts as chip select input (level sensitive, active low). when low, the ad5381 is selected. serial interface mode. this is the frame synchronization input signal for the serial clock and data. i 2 c mode. this pin acts as a hardware address pin used in conjunction with ad1 to determine the software address for the device on the i 2 c bus. wr /(dcen/ad1) multifunction pin. in parallel interface mode, this pin acts as write enable. in serial interface mode, th is pin acts as a daisy - chain enable in spi mode and as a hardware address pin in i 2 c mode. parallel interface write input (edge sensitive). the rising edge of wr is used in conjunction with cs low , and the address bus inputs to write to the selected device registers. serial interface. daisy - chain select input (level sensitive, active high). when high, this signal is used in conjunction with ser/ par high to enable the spi serial interface daisy - chai n mode. i 2 c mode. this pin acts as a hardware address pin used in conjunction with ad0 to determine the software address for this device on the i 2 c bus. db11 C db0 parallel data bus. db11 is the msb and db0 is the lsb of the input data - word on the ad53 81. a5 Ca0 parallel address inputs. a5 to a0 are decoded to address one of the ad5381s 40 input channels. used in conjunction with the reg1 and reg0 pins to determine the destination register for the input data. reg1, reg0 in parallel interface mode , re g1 and reg0 are used in decoding the destination registers for the input data. reg1 and reg0 are decoded to address the input data register, offset register, or gain register for the selected channel and are also used to decide the special function registe rs. sdo /( a /b) serial data output in serial interface mode. three - stateable cmos output. sdo can be used for daisy - chaining a number of devices together. data is clocked out on sdo on the rising edge of sclk, and is valid on the falling e dge of sclk. when operating in parallel interface mode, this pin acts as the a or b data register select when writing data to the ad5381s data registers with toggle mode selected (see the toggle mode function section). in toggle mode, the ldac is used to switch the output between the data contained in the a and b data registers. all dac channels contain two data registers. in normal mode, data register a is the default for data transfers. busy digital cmos output. busy goes low during internal calculations of the data (x2) loaded to the dac data register. during this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the dac registers and dac outputs can take place. if ldac is taken low while busy is low, this event is stored. busy also goes low during power - on reset, and when the reset pin is low. during this time, the interface is disabled and a ny events on ldac are ignored. a clr operation also brings busy low. ldac load dac logic input (active low). if ldac is taken low while busy is i nactive (high), the contents of the input registers are transferred to the dac registers and the dac outputs are updated. if ldac is taken low while busy is active and internal calculations are taking place, the ldac event is stored and the dac registers are updated when busy goes inactive. however any events on ldac during power - on reset or on reset are ignored. clr asynchronous c lear input. the clr input is falling edge sensitive. when clr is activated, all channels are updated with the data contained in the clr code register. busy is low for a duration of 35 s while all channels are being updated with the clr code. reset asynchronous digital reset input (falling edge sensitive). the function of this pin is equivalent to that of the power - on reset generator. when this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power - on values. this sequence typically takes 270 s. the falling edge of reset initiates the re set process and busy goes low for the duration, returning high when reset is complete. while busy is low, all interfaces are disabled and all ldac pulses are ignored. when busy returns high, the part resumes normal operation and the status of the reset pin is ignored until the next falling edge is detected.
ad5381 data sheet rev. d | page 16 of 40 mnemonic function pd power - down (level sensitive, active high). pd is used to place the device in low power mode , where the analog current consum ption is reduced to 2 a and the digital current consumption is reduced to 20 a . in power - down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance ou tput or provide s a 100 k? load to ground, depending on how the power - down mode is configured. the serial interface remains active during power - do wn. fifo en fifo enable (level sensitive, active high). when connected to dvdd, the internal fifo is enabled, allowing the u ser to write to the device at full speed. fifo is only available in parallel interface mode. the status of the fifo en pin is sampled on power - up, and also following a clear or reset, to determine if the fifo is enabled. in either serial or i 2 c interface modes, the fifo en pin should be tied low. db9/ ( spi / i 2 c ) multifunction input pin. in parallel interface mode, this pin acts as db9 of the parallel input data - word. in serial interface mode, this pin acts as serial interface mode select. when serial interface mode is selected (ser/ par = 1) and this input is low, spi mode is selected. in spi mode, db12 is the serial clock (sclk) input and db11 is the serial data (din) input. when serial interface mode is selected (ser/ par = 1) and this input is high i 2 c mode is selected. in this mode, db12 is the serial clock (scl) input and db11 is the serial data (sda) input. db10/ (sclk/scl) multifunction input pin. in parallel interface mode, this pin acts as db 10 of the parallel input data - word. in serial interface mode, this pin acts as a serial clock input. serial interface mode. in serial interface mode, data is clocked into the shift register on the falling edge of sclk. this operates at clock speeds up t o 50 mhz. i 2 c mode. in i 2 c mode, this pin performs the scl function, clocking data into the device. the data transfer rate in i 2 c mode is compatible with both 100 khz and 400 khz operating modes. db11/(din/sda) multifunction data input pin. in paralle l interface mode, this pin acts as db11 of the parallel input data - word. serial interface mode. in serial interface mode, this pin acts as the serial data input. data must be valid on the falling edge of sclk. i 2 c mode. in i 2 c mode, this pin is the se rial data pin (sda) operating as an open - drain input/output.
data sheet ad5381 rev. d | page 17 of 40 terminology relative accuracy relative accuracy , or endpoint linearity , is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function . it is measured after adjusting for zero - scale error and full - scale error , and is expressed in lsb . differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent code s. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero - scale error zero - scale error is the error in the dac output voltage when all 0s are loaded into the dac register. ideally, with all 0s loaded to the dac and m = all 1s, c = 2 n C 1 vout ( zero - sc ale ) = 0 v zero - scale error is a measure of the difference between vout (actual) and vout (ideal) , expressed in mv. it is mainly due to offsets in the output amplifier. offset error offset error is a measure of the difference between v out (actual) and vout (ideal) in the linear region of the transfer function, expressed in mv. offset error is measured on the ad5381 - 5 with code 32 loaded into the dac register , and on the ad5381 - 3 with c ode 64. gain error gain error is specified in the li near region of the output range between vout = 10 mv and vout = avdd C 50 mv. it is the deviation in slope of the dac transfer characteristic from the ideal and is expressed in %fsr with the dac output unloaded. dc crosstalk this is the dc change in the o utput level of one dac at midscale in response to a full - scale code (all 0 s to all 1s, and vice versa) and output change of all other dacs. it is expressed in lsb . dc output impedance this is the effective output source resistance. it is dominated by pack age lead resistance. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input change , and is measured from the busy rising edge. digital - to - analo g glitch energy this is the amount of energy injected into the analog output at the major code transition. it is specified as the area of the glitch in nv - s. it is measured by toggling the dac register data between 0x 7 ff and 0x 8 00. dac - to - dac crosstalk dac - to - dac crosstalk is the glitch impulse that appears at the output of one dac due to both the digital change and the subsequent analog output change at another dac. the victim channel is loaded with m idscale. dac - to - dac crosstalk is specified in nv - s. digi tal crosstalk the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter is defined as the digital crosstalk and is specified in nv - s. digital feedthrough when the device is not selected, hig h frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the vout pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. outp ut noise spectral density this is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per hertz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/ hz in a 1 hz bandwidth at 10 k hz .
ad5381 data sheet rev. d | page 18 of 40 typical performance characteristics 03732-009 input code 4096 0 512 1024 1536 2048 2560 3072 3584 inl error (lsb) 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 avdd = 5v refin = 2.5v t a = 25c figure 9 . typical ad5381 - 5 inl plot 2.510 2.505 2.500 2.995 2.990 0 12 10 8 6 4 2 voltage (v) time (s) 03732-103 f igure 10. ad5381 - 5 glitch impulse 03732-011 ldac vout avdd = dvdd = 5v v ref = 2.5v t a = 25c figure 11 . slew rate with boost off 03732-012 input code 4096 0 512 1024 1536 2048 2560 3072 3584 inl error (lsb) 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 avdd = 3v refin = 1.25v t a = 25c figure 12. typical ad5381 - 3 inl plot 03732-013 sample number 550 0 100 150 200 250 300 50 350 400 500450 amplitude (v) 1.245 1.254 1.253 1.252 1.251 1.250 1.249 1.248 1.247 1.246 avdd = dvdd = 3v v ref = 1.25v t a = 25c 14ns/sample number 1 lsb change around midscale glitch impulse = 5nv-s figure 13. ad5381 - 3 glitch impulse 03732-014 ldac vout avdd = dvdd = 5v vref = 2.5v t a = 25c figure 14 . slew rate with boost on
data sheet ad5381 rev. d | page 19 of 40 03732-015 ai dd (ma) 11 8 9 10 percentage of units (%) 14 12 10 8 6 4 2 avdd = 5.5v v ref = 2.5v t a = 25c figure 15 . ai dd histogram with boost off 03732-107 di dd (ma) 0.9 1.0 0.5 0.6 0.7 0.8 number of units 0 10 8 6 4 2 dvdd = 5.5v v ih = dvdd v il = dgnd t a = 25c figure 16 . di dd histogram 03732-017 busy vout avdd = dvdd = 5v v ref = 2.5v t a = 25c figure 17 . exiting soft power - down 03732-102 vdd vout avdd = dvdd = 5v vref = 2.5v t a = 25c figure 18 . power - up transient 03732-019 reference drift (ppm/c) ?5.0 ?1.5 2.5 ?3.5?4.5 ?4.0 0.5?0.5 3.5 ?2.5 1.5 ?1.0 3.0 ?3.0 1.00 4.0 5.0 4.5 ? 2.0 2.0 frequency 0 40 30 20 35 25 15 10 5 figure 19 . refout temperature coefficient 03732-020 pd vout avdd = dvdd = 5v v ref = 2.5v t a = 25c figure 20 . exiting hardware power - down
ad5381 data sheet rev. d | page 20 of 40 03732-021 current (ma) ?40 ?20 ?10 ?5 ?2 0 2 5 10 20 40 vout (v) ?1 6 4 3 2 5 1 0 zero scale 1/4 scale midscale 3/4 scale ful l scale a vdd = dvdd = 5v v ref = 2.5v t a = 25c figure 21. ad5381 - 5 output amplifier source and sink capability 03732-022 i source /i sink (ma) 2.00 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 error voltage (v) ?0.20 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.15 avdd = 5v v ref = 2.5v t a = 25c error at zero sinking current (vdd?vout) at full-scale sourcing current figure 22 . headroom at rails vs. source/sink current 03732-023 frequency (hz) 100k 100 1k 10k output noise (nv/ hz) 0 600 500 400 300 200 100 avdd = 5v t a = 25 c refout decoupled with 100nf capacitor refout = 2.5v refout = 1.25v figure 23 . refout noise spectral density 03732-024 current (ma) ?40 ?20 ?10 ?5 ?2 0 2 5 10 20 ?40 vout (v) ?1 6 4 3 2 5 1 0 zero scale 1/4 scale midscale 3/4 scale ful l scale a vdd = dvdd = 3v v ref = 1.25v t a = 25c figure 24. ad5381 - 3 output amplifier source and sink capability 03732-025 sample number 550 0 100 150 200 250 300 50 350 400 500450 amplitude (v) 2.449 2.456 2.455 2.454 2.453 2.452 2.451 2.450 avdd = dvdd = 5v v ref = 2.5v t a = 25c 14ns/sample number figure 25 . adjacent channel dac - to - dac crosstalk av dd = dv dd = 5v v ref = 2.5v t a = 25c exits soft pd to midscale 03732-026 avdd = dvdd = 5v t a = 25c dac loaded with midscale external reference y axis = 5 v/div x axis = 100ms/div figure 26. 0.1 hz to 10 hz noise plot
data sheet ad5381 rev. d | page 21 of 40 functional descripti on dac architecture general the ad5381 is a complete , s ingle - supply, 40 - channel voltage output dac that offers 12 - bit resolution . the part is available in a 100 - lead lqfp package and features both a parallel and a serial interface. this product includes an internal , software selectable , 1.25 v /2.5 v, 1 0 ppm/c reference that can be used to drive the buffered reference inputs ; alternatively , an external reference can be used to drive these inputs. internal/external r eference selection is via the cr 8 bit in the control register ; cr1 0 selects the reference magnitude if the internal reference is selected . all channels have an on - chip output amplifier with rail - to - rail output capable of driving 5 k? in parallel with a 200 pf load. 03732-027 vout r r 12-bit dac dac reg m reg c reg 1 input reg 2 input data vref avdd figure 27 . single - channel architecture the architecture of a single dac channel consists of a 1 2- bit resistor - string dac followed by an output buffer amplifier operating at a gain of 2 . this res istor - string architecture guarantees dac monotonicity. the 12 - bit binary digital code loaded to the dac register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. each channel on these devices contain s independ e nt offset and gain control registers that allow the user to digitally trim offset and gain. t hese registers give the user the ability to calibrate out errors in the complete signal chain , including the dac , using the internal m and c registers , which hold the correction factors. all channels are double buffered , allow - ing synchronous updating of all channels using the ldac pin. figure 27 shows a block diagram of a single channel on the ad 5381 . the digital input transfer function for e ach d ac can be represented as x2 = [( m + 2 )/ 2 n x1 ] + ( c C 2 n C 1 ) where: x2 = the d ata - word loaded to the resistor string dac . x1 = the 12 - bit d ata - word written to the dac input register . m = the g ain c oef ficient (default is 0x ff e) . the gain coefficient is written to the 11 most significant bits (db11 to db1), the lsb (db0) of the data - word is a 0. n = dac resolution ( n = 12 for ad5381 ). c = the 12 - bit o ffset c oefficient (default is 0x800 ). the complete tra nsfer function for thes e devices can be represented as vout = 2 v ref x2 /2 n where: x2 is the d ata - word loaded to the resistor string dac . v ref is externally applied to the dac refout/refin pin. for specified performance , an external reference voltage of 2.5 v is recommended for the ad5381 -5, and 1.25 v for the ad5381 -3. data decoding the ad5381 contains a 12 - bit data bus, db11 to db0. depend - ing on the value of reg1 and reg0 (see ta b le 10 ) , this data is loaded into the addressed dac input registers, o ffset (c) registers, or g ain (m) registers. the format data, o ffset (c) , and gain (m) register contents are shown in ta b le 11 to ta b le 13 . table 10 . register se lection reg1 reg0 register selected 1 1 input data register (x1) 1 0 offset register (c) 0 1 gain register (m) 0 0 special function registers (sfrs) table 11 . dac data f ormat (reg1 = 1, reg0 = 1) db11 to db0 dac ou tput (v) 1111 1111 1111 2 v ref (4095/4096) 1111 1111 1110 2 v ref (4094/4096) 1000 0000 0001 2 v ref (2049/4096) 1000 0000 0000 2 v ref (2048/4096) 0111 1111 1111 2 v ref (2047/4096) 0000 0000 0001 2 v ref (1/4096) 0000 0000 0000 0 tab le 12 . offset data f ormat (reg1 = 1, reg0 = 0) db11 to db0 offset (lsb) 1111 1111 1111 +2048 1111 1111 1110 +2047 1000 0000 0001 +1 1000 0000 0000 0 0111 1111 1111 C 1 0000 0000 0001 C2047 0000 0000 0000 C 2048 table 13 . gain data f ormat (reg1 = 0, reg0 = 1) db11 to db 0 gain factor 1111 1111 1110 1 1011 1111 1110 0.75 0111 1111 1110 0.5 0011 1111 1110 0.25 0000 0000 0000 0
ad5381 data sheet rev. d | page 22 of 40 on -c hip special function registers (sfr) the ad5381 contains a number of special function registers (sfrs) , as outlined in ta b le 14 . sfrs are addressed with reg1 = reg0 = 0 and are decoded using a ddress b its a5 to a0. table 14 . sfr register functions (reg1 = 0, re g0 = 0) r/ w a5 a4 a3 a2 a1 a0 function x 0 0 0 0 0 0 nop (no operation) 0 0 0 0 0 0 1 write clr code 0 0 0 0 0 1 0 soft clr 0 0 0 1 0 0 0 soft power - down 0 0 0 1 0 0 1 soft power - up 0 0 0 1 1 0 0 control regist er write 1 0 0 1 1 0 0 control register read 0 0 0 1 0 1 0 monitor channel 0 0 0 1 1 1 1 soft reset sfr commands nop (n o o peration) reg1 = reg0 = 0, a5 to a0 = 000000 performs no operation but is useful in serial readback mode to clock out data on d out for diagnostic purposes. busy pulses low during a nop operation. write clr code reg1 = reg0 = 0, a5 to a0 = 000001 db11 to db0 = contain the clr data bringing the clr line low or exercising the soft clear f unction will load the contents of the dac registers with the data con - tained in the user configurable clr register , and will set vout0 to vout39 accordingly. this can be very useful for setting up a specific output voltage in a clear condition . it is also beneficial for calibration purposes ; the user can load full scale or zero scale to the clear code register and then issue a hard - ware or software clear to load this code to all dac s, removing the need for individual writes to each dac. default on power - up is all zeros. soft clr reg1 = reg0 = 0, a5 to a0 = 000010 db11 to db0 = don t care executing this instruction performs the clr , which is func - tionally the same as that provided by the external clr pin. the dac outputs are loaded with the data in the clr code register. it takes 35 s to fully execute the soft clr, as indicated by the busy low time. soft power - down reg1 = reg0 = 0, a5 to a0 = 001000 db11 to db0 = don t care executing this instruction performs a global powe r- down feature that puts all channels into a low power mode that reduc es the analog supply current to 2 a max and the digi - tal current to 20 a max . in power - down mode , the output amplifier can be configured as a high impedance output or provide a 100 k? load to ground. the contents of all internal registers are retained in power - down mode. no register can be written to while in power - down. soft power -up reg1 = reg0 = 0, a5 to a0 = 001001 db11 to db0 = don t care this instruction is used to power up the output amplifiers and the internal reference. the time to exit power - down is 8 s. the hardware power - down and software function are internally combined in a digital or function. soft reset reg1 = reg0 = 0, a5 to a0 = 001111 db11 to db0 = don t care this ins truction is used to implement a software reset. all internal registers are reset to their default values , which corre - spond to m at full scale and c at zero scale . the contents of the dac registers are cleared , setting all analog outputs to 0 v . the soft r eset activation time is 1 35 s.
data sheet ad5381 rev. d | page 23 of 40 table 15 . control register contents msb lsb cr11 cr10 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 control register write/read reg1 = reg0 = 0, a5 to a0 = 001100, r/ w stat us determines if the operation is a write (r/ w = 0) or a read (r/ w = 1). db11 to db0 contains the control register data. control register contents cr1 1: power - down status. this bit is used to configure the output amplif ier state in power - down . cr1 1 = 1. a mplifier output is high impedance (de fault o n power - up) . cr11 = 0 . a mplifier output is 100 k? to ground . cr1 0: ref select. this bit selects the operating internal reference for the ad5381 . cr1 0 is programmed as follows: cr1 0 = 1: internal reference is 2.5 v ( ad5381 - 5 default) , the r ecommended operating reference for ad5381 - 5. cr1 0 = 0: internal r eferen ce is 1.25 v ( ad5381 - 3 default), the r ecommended operating reference for ad5381 - 3. cr 9: current boost control. this bit is used to boost the current in the output amplifier , ther e by altering its slew rate. this bit is configured as follows: cr 9 = 1: boost m ode o n. this maximizes the bias current in the output amplifier , optimizing its slew rate but increasing the power dissipation. cr 9 = 0: boost m ode o ff ( d efault on power - up). this reduces the bias current in the output amplifier and reduces the over all power consumption. cr 8: internal/external reference. this bit determines if the dac uses its internal reference or an externally applied reference. cr 8 = 1: internal reference e nable d. the r e ference output depends on data loaded to cr1 0. cr 8 = 0: exter nal reference s elected (default on power - up) . cr 7: channel monitor enable (see channel monitor function section ). cr 7= 1: monitor enabled. this enables the channel monitor function. after a write to the monitor chan nel in the sfr register , the selected channel outp ut is routed to the mon_out pin . vout 39 operates at the mon_out pin. cr 7 = 0: monitor disabled (default on power - up). when the monitor is disabled , the mon_out pin assumes its normal dac output function. cr6: thermal monitor function. w hen enabled , t his function is used to monitor the internal die temperature of the ad5381 . the thermal monitor powers down the output amplifiers when the temperature exceeds 130 c. this function can be used to protect the devi ce in cases where power dissipation may be exceeded if a number of output channels are simultaneously short - circuited. a soft power - up will re - enable the output amplifiers i f the die temperature has dropped below 130 c. cr 6 = 1: thermal m onitor e nable d. cr 6 = 0: thermal m onitor d isabled (default on power - up). cr 5: d o nt c a re . cr 4 to cr 0: toggle function enable. this function allows the user to toggle the output between two codes loaded to the a and b register s for each dac. control r egister b its cr 4 to cr 0 are used to enable individual groups of eight channels for operation in toggle m ode. a l ogic 1 written to any bit enables a group of channels ; a l ogic 0 disables a group. ldac is used to toggle between the two registers. table 16 . cr bit group channels cr4 4 32C39 cr3 3 24C31 cr2 2 16C23 cr1 1 8C 15 cr0 0 0C7 channel monitor function reg1 = reg0 = 0, a5 to a0 = 001010 db11 C db 6 = contain data to address the monitored channel. a channel monitor function is provided on the ad5381 . t his feature , which consist s of a multiplexer addressed via the inter - face , allows any channel output to be routed to th e mon_out pin for monitoring using an external adc. in channel monitor mode , vout 39 becomes the mon_out pin, to which all monitored pins are routed. the channel monitor function must be enabled in the control register before any channels are routed to mon_out. on the ad5381 , db11 to db 6 contain the channel address for the monitored channel. selecting c hannel a ddres s 63 three - states m o n _ o u t.
ad5381 data sheet rev. d | page 24 of 40 table 17. ad5381 channel monitor decoding reg1 reg0 a5 a4 a3 a2 a1 a0 db 11 db10 db9 db8 db8 db6 db5Cdb0 mon_out 0 0 0 0 1 0 1 0 0 0 0 0 0 0 x vout0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 x vout1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 x vout2 0 0 0 0 1 0 1 0 0 0 0 0 1 1 x vout3 0 0 0 0 1 0 1 0 0 0 0 1 0 0 x vout4 0 0 0 0 1 0 1 0 0 0 0 1 0 1 x vout5 0 0 0 0 1 0 1 0 0 0 0 1 1 0 x vout6 0 0 0 0 1 0 1 0 0 0 0 1 1 1 x vout7 0 0 0 0 1 0 1 0 0 0 1 0 0 0 x vout8 0 0 0 0 1 0 1 0 0 0 1 0 0 1 x vout9 0 0 0 0 1 0 1 0 0 0 1 0 1 0 x vout10 0 0 0 0 1 0 1 0 0 0 1 0 1 1 x vout11 0 0 0 0 1 0 1 0 0 0 1 1 0 0 x vout12 0 0 0 0 1 0 1 0 0 0 1 1 0 1 x vout13 0 0 0 0 1 0 1 0 0 0 1 1 1 0 x vout14 0 0 0 0 1 0 1 0 0 0 1 1 1 1 x vout15 0 0 0 0 1 0 1 0 0 1 0 0 0 0 x vout16 0 0 0 0 1 0 1 0 0 1 0 0 0 1 x vout17 0 0 0 0 1 0 1 0 0 1 0 0 1 0 x vout18 0 0 0 0 1 0 1 0 0 1 0 0 1 1 x vout19 0 0 0 0 1 0 1 0 0 1 0 1 0 0 x vout20 0 0 0 0 1 0 1 0 0 1 0 1 0 1 x vout21 0 0 0 0 1 0 1 0 0 1 0 1 1 0 x vout22 0 0 0 0 1 0 1 0 0 1 0 1 1 1 x vout23 0 0 0 0 1 0 1 0 0 1 1 0 0 0 x vout24 0 0 0 0 1 0 1 0 0 1 1 0 0 1 x vout25 0 0 0 0 1 0 1 0 0 1 1 0 1 0 x vout26 0 0 0 0 1 0 1 0 0 1 1 0 1 1 x vout27 0 0 0 0 1 0 1 0 0 1 1 1 0 0 x vout28 0 0 0 0 1 0 1 0 0 1 1 1 0 1 x vout29 0 0 0 0 1 0 1 0 0 1 1 1 1 0 x vout30 0 0 0 0 1 0 1 0 0 1 1 1 1 1 x vout31 0 0 0 0 1 0 1 0 1 0 0 0 0 0 x vout32 0 0 0 0 1 0 1 0 1 0 0 0 0 1 x vout33 0 0 0 0 1 0 1 0 1 0 0 0 1 0 x vout34 0 0 0 0 1 0 1 0 1 0 0 0 1 1 x vout35 0 0 0 0 1 0 1 0 1 0 0 1 0 0 x vout36 0 0 0 0 1 0 1 0 1 0 0 1 0 1 x vout37 0 0 0 0 1 0 1 0 1 0 0 1 1 0 x vout38 0 0 0 0 1 0 1 0 1 0 0 1 1 1 x undefined ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 1 0 1 0 1 1 1 1 1 0 x undefined 0 0 0 0 1 0 1 0 1 1 1 1 1 1 x three-state 03732-028 db11?db6 channel address ad5381 channel monitor decoding 00001010 vout0 vout1 vout37 vout38 vout39/mon_out reg1 reg0 a5 a4 a3 a2 a1 a0 figure 28. channel monitor decoding
data sheet ad5381 rev. d | page 25 of 40 hardware functions reset function bringing the reset line low resets the contents of all internal registers to their power - on reset stat e. reset is a negative edge - sensitive input. the default corresponds to m at full - scale and to c at zero scale . the contents of the dac registers are cleared , setting vout0 to vout39 to 0 v . this sequence takes 270 s . the falling edge of re set initiates the reset process ; busy goes low for the duration , returning high when reset is complete. while busy is low , all interfaces are disabled and all ldac pulses are ignored. when busy re turns high , the part resumes normal operation and the status of the reset pin is ignored until the next falling edge is detected. asynchronous clear f unction bringing the clr line low clears the contents o f the d ac registers to the data contained in the user configurable clr register and sets vout0 to vout39 accordingly. this func - tion can be used in system calibration to load zero - scale and full - scale to all channels. the execution time for a clr is 3 5 s. busy and ldac functions busy is a digital cmos output that indicates the status of the ad5381 . the value of x2 , the internal data loaded to the dac data register , is calculated each time the user write s new data to the corresponding x1, c , or m registers. during the calculation of x2 , the busy output goes low. while busy is low , the user can continue writing new data to the x1, m , or c registers , but no dac output upd ates can take place. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs update immediately af ter busy goes high. the user may hold the ldac input permanently low , in which case the dac outputs update immediately after busy goes high. busy also goes low during power - on reset an d when a falling edge is detected on the reset pin. during this time , all interfaces are disabled and any events on ldac are ignored. the ad5381 contains an extra feature whereby a dac register is not updated unless its x2 register has been written to since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2 registers. however , the ad5381 will only update the dac register if the x2 data has changed, thereby removing unnecessary digital crosstalk. fifo operation in pa rallel m ode the ad5381 contains a fifo to optimize operation when operating in parallel interface mode. the fifo enable (level sensitive , active high) is used to enable the internal fifo. when connected to dv dd , the internal fifo is enabled , allowing the user to write to the device at full speed. fifo is only available in parallel interfa ce mode. the status of the fifo en pin is sam - pled on power - up, and after a clr or reset , to determine if the fifo is enabled. in either serial or i 2 c interface modes , fifo en should be tied low. up to 128 successive instructions can be written to the fifo at maximum speed in par allel mode. when the fifo is full , any further writes to the device are ignored. figure 29 shows a comparison between fifo mode and non - fifo mode in terms of channel update time . figure 29 also outlines digital loading time. number of writes time (s) 1 4 7 10 13 16 19 22 25 28 31 34 37 0 10 5 15 25 20 40 without fifo (channel update time) with fifo (channel update time) with fifo (digital loading time) 03732-029 figure 29 . channel update rate (fifo vs . non - fifo) power - on reset the ad5381 contains a power - on reset generator and state machine. the power - on reset resets all registers to a p redefined state and configures the analog outputs as high impedance. the busy pin goes low during the power - on reset sequencing , pre - venting data writes to the device. power - down the ad5381 contains a global power - down feature that puts a ll channels into a low power mode and reduces the analog power consumption to 2 a max and digital power consumption to 20 a max. in power - down mode , the output amplifier can be configured as a high impedance output or can provide a 100 k? load to ground. the contents of all internal registers are retained in power - down mode. when exiting power - down , the settling time of the amplifier will elapse before the outputs settle to their correct value s.
ad5381 data sheet rev. d | page 26 of 40 interfaces the ad5381 contains both parallel and serial i nterfaces. furthermore, the serial interface can be programmed to be either spi - , dsp -, microwire -, or i 2 c- compatible. the ser/ pa r pin selects parallel and serial interface modes. in serial mode , the spi /i 2 c pin is used to select dsp -, spi -, microwire -, or i 2 c- interface mode. the devices use an internal fifo memory to allow high speed successive writes in parallel interface mode. the user can con - tinue writing new data to the device while write instructions are being exec uted. the busy signal indicates the current status of the device, going low while instructions in the fifo are being executed. in parallel mode, u p to 128 successive instructions can be written to the fifo at maximum speed. when the fifo is full , any further writes to the device are ignored. to minimize both the power consumption of the device and the on - chip digital noise, the active interface only powers up fully when the device is being written to, that is , on the falling edge of wr or the falling edge of sync . dsp - , spi - , microwire - compatible serial interfaces the serial interface can be operated with a minimum of three wires in standalone mode or four wires in daisy - chain mode. daisy chaining allows many devices to be cascaded together to increase system channel count. the ser/ pa r pin must be tied high and the spi /i 2 c pin (p in 97) should be tied low to enable the dsp -/ spi -/ microwire - compatible serial interface. in s erial interface mode , the user does not need to drive the paral - lel input data pins. the serial interface s control pins are sync , din, sclk standard 3 -w ire i nterface p ins . dcen selects s tand a lo ne m ode or d aisy -c hain m ode. sdo data o ut p in for daisy -c hain m ode. figure 3 and figure 5 show timing diagram s for a serial write to the ad5381 in s tand a lone and d aisy -c hain m ode s . the 24- bit data - word format for the serial interface i s shown in ta b le 18 . a /b t his pin selects whether the data write is to the a or b register w hen toggle mode is enabled . w ith t oggle disabled , this bit should be set to 0 to selec t the a data register. r/ w is the r ead or w rite control bit. a5 to a0 are used to a ddress the input chann els. reg1 and reg0 s elect the register to which data is written , as shown in ta b le 10 . db11 to . db0 c ontain the input data - word. x is a don t care condition. stand a lone mode by connecting the dcen ( d aisy -c hain e nable) pin low, s tand - a lone m ode is enabled. the serial interface works with both a continuous and a noncontinuous serial clock. the firs t falling edge of sync starts the write cycle and resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted into the serial shift register. any further edges on sync , excep t for a falling edge , are ignored until 24 bits are clocked in. once 24 bits are shifted in, the sclk is ignored. in order for another serial transfer to take place , the counter must be reset by the falling edge of sync . table 18 . 40 - channel, 12 - bit dac serial input register configuration msb lsb a /b r/ w a5 a4 a3 a2 a1 a0 reg1 reg0 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 x x
data sheet ad5381 rev. d | page 27 of 40 daisy - chain mode for systems that contain several devices, the sdo pin can be used to daisy - chain several devices together. this daisy - chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. by connecting the dcen ( da isy -c hain e nable) pin high, daisy - chain mode is enabled. the first falling edge of sync starts the write cycle. the sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the din input on the next device in the chain, a multidevice interface is constructed. twenty - four clock pulses are required for each device in the system. therefore, the total number of clock cycles must equal 24n, where n is the total number of ad538x devices in the chain. when the serial transfer to all devices is complete, sync is taken high. this latches the input data in each device in the daisy - chain and prevents further data from being clocked into the input shift register. if sync is taken high before 24 clocks are clocked into the part, this is considered a bad frame and the data is discarded. the serial clock can be either a continuous or a gated clock. a continuous sclk source can only be used if it can be arranged that sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used and sync must be taken high after the final clock to latch the data. readback mode readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. with r/ w = 1, b its a5 to a0 , in association with b its reg1 and reg0 , select the register to be read. the remaining data bits in the write sequence ar e don t cares. during the next spi write , the data appearing on the sdo output will contain the data from the previously addressed register. for a read of a single register , the nop command can be used in clocking out the data from the selected register o n sdo. figure 30 shows the readback sequence. for example, to read back the m register of c hannel 0 on the ad5381 , the following sequence should be implemented. first , write 0x 404xxx to the ad5381 input register. th is configures the ad5381 for read mode with the m register of c hannel 0 selected. note that d ata b its db11 to db0 are don t cares. follow this with a second write, a nop condition, 0x000000 . d uring this write , the data from the m register is clocked out o n the dout line, that is , data clocked out will contain the data from the m register in b it db11 to bit db0, and the top 10 bits contain the address information as previously written. in readback mode , the sync signal must frame the data. data is clocked out on the rising edge of sclk and is valid on the falling edge of the sclk signal. i f the sclk idles high between the write and read operations of a readback operation , the first bit of data is clocked out on the falling edge of sync . 03732-030 24 48 sclk sync din sdo undefined selected register data clocked out nop condition input word specifies register to be read db23 db0 db0 db23 db23 db0 db0 db23 figure 30 . serial readback operation
ad5381 data sheet rev. d | page 28 of 40 i 2 c serial interface the ad5381 features an i 2 c- compatible 2 - wire interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate co mmunication between the ad5381 and the master at rates up to 400 khz. figure 6 show s the 2 - wire interface timing diagrams that incorporate three different modes of operation. in selecting the i 2 c operating mode , fir st configure serial operating mode (ser/ pa r = 1) and then select i 2 c mode by configuring the spi /i 2 c pin to a l ogic 1 . the device is connected to t he i 2 c bus as a slave device ( that is, no clock is generated by the ad538 1 ). the ad5381 has a 7 - bit slave address 1010 1 ( ad1 )( ad0 ) . the 5 msb are hard - coded and the 2 lsb are determined by the state of the ad1 and ad0 pins. the facility to hardware configure ad1 and ad0 allows four of these devices to be configured on the bus. i 2 c data transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals that configure start and stop c onditions. both sd a and scl are pulled high by the external pull - up resistors when the i 2 c bus is not busy. start and stop conditions a master device initiates communication by issuing a start condition. a start condition is a high - to - low transition on sda with scl high. a stop condition is a low - to - high transition on sda while scl is high. a start condition from the master signals the beginning of a transmission to the ad5381 . the stop condition frees the bus. if a repeated start condition (sr) is generated instead of a stop condition, the bus remains active. repeated start conditions a repeated start (sr) condition may indicate a change of data direction on the bus. sr can be used when the bus master is writing to several i 2 c devices and want s to maintain control of the bus. acknowledge bit (ack) the acknowledge bit (ack) is the ninth bit attached to any 8- bit data - word. ack is always generated by the receiving device. the ad5381 devices generate an ack when receiving an address or data by pulling sda low during the ninth clock period. monitoring ack allows for detection of unsuccess - ful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should r eattempt communication. ad5381 slave addresses a bus master initiates communication with a slave device by issuing a start condition followed by the 7 - bit slave address. when idle, the ad5381 waits for a start condition followed by its slave address. the lsb of the address word is the read/ write (r/ w ) bit. the ad5381 is a receive only device ; w hen communicating with the ad5381 , r/ w = 0. after receiving the proper address 1010 1 ( ad1 )( ad0 ) , the ad5381 issues an ack by pul ling sda low for one clock cycle. the ad5381 has four different user programmable addresses determined by the ad1 and ad0 bits. write operation there are three specific modes in which data can be written to the ad5381 dac . 4- byte mode when writing to the a d5381 dacs, the user must begin with an address byte (r/ w = 0) after which the dac acknowl - edge s that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte ; this addresses the specific channel in the dac to be addressed and is also acknowledged by the dac. two bytes of data are then written to the dac , as shown in figure 31 . a stop condition follows. this allows the user to update a single channel within the ad5381 at any time and requires four bytes of data to be transferred from the master. 3- byte mode in 3 - byte mode, t he user can update more than one channel in a write sequence without having to write the device address byte each time. the device addre ss byte is only required once; sub - sequent channel updates require the pointer byte and the data bytes. in 3 - byte mode, the user begins with an address byte (r/ w = 0), after which the dac will acknowledge that it is pre - pared to receive d ata by pulling sda low. the address byte is followed by the pointer byte. this addresses the specific channel in the dac to be addressed and is also acknowledged by the dac. this is then followed by the two data bytes. reg1 and reg0 determine the register to be updated. if a stop condition does not follow the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. this mode only requires three bytes to be sent to update any channel once the device has been initia lly addressed, and reduces the software overhead in updating the ad5381 channels. a stop condition at any time exits this mode. figure 32 shows a typical configuration.
data sheet ad5381 rev. d | page 29 of 40 1 0 1 0 1 ad1 ad0 r/w 0 0 a5 a4 a3 a2 a1 a0 scl sda scl sda st art cond by master ack b y ad538x ack b y ad538x address byte most significant byte least significant byte pointer byte msb ack b y ad538x ack b y ad538x stop cond by master reg1 reg0 msb lsb msb lsb 03732-031 figure 31 . 4 - byte ad5381, i 2 c write operation scl sda sda scl sda scl sda scl start cond by master ack by ad538x msb address byte pointer byte for channel "n" most significant data byte pointer byte for channel "next channel" least significant data byte most significant data byte least significant data byte ack by ad538x ack by ad538x data for channel "n" data for channel "next channel" ack by ad538x 1 0 0 a5 a4 a3 a2 a1 a0 0 1 0 0 0 a5 a4 a3 a2 a1 a0 1 ad1 ad0 r/w reg1 reg0 msb lsb msb lsb msb ack by ad538x ack by ad538x ack by ad538x stop cond by master reg1 reg0 msb lsb msb lsb figure 32 . 3 - byte ad5381 , i 2 c write operation
ad5381 data sheet rev. d | page 30 of 40 2- byte mode following initialization of 2- byte mode , the user can update channels sequentially. the device address byte is only required once and th e pointer address pointer is configured for auto - increment or burst mode. the user must begin with an address byte (r/ w = 0) , after which the dac acknowledge s that it is prepared to receive data by pulling sda low. the address byte is fol lowed by a specific pointer byte ( 0x ff) that initiates the burst mode of operation. the address pointer initializes to c hannel 0, the data following the pointer is loaded to c hannel 0, and the address pointer automatically increments to the next address. t he reg0 and reg1 bits in the data byte determine which register will be updated. in this mode, following the initializa - tion , only the two data bytes are required to update a channel . t he channel address automatically increments from a ddress 0 to c hannel 39 and then returns to the normal 3 - byte mode of operation. this mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. a stop condition at any time exits this mode. toggle mode is not su pported in 2 -b yte m o de . figure 33 shows a typical configuration. parallel interface the ser/ pa r pin must be tied low to enable the parallel interface and disable the serial interfaces. figure 7 shows the timing diagram for a parallel write. the parallel interface is controlled by the following pins . cs pin active l ow d evice s elect p in. wr pin on the rising edge of wr , with cs low, the addresses on pin a5 to pin a0 are latched; data present on the data bus is loaded into the selected input registers. reg0, reg1 pins the reg0 and reg1 pins determine the destination register of the data being written to the ad5381 . see ta b le 10 . pin a5 to pin a0 each of the 40 dac channels can be individually addressed. pin db11 to pin db0 the ad5381 accepts a straight 12 - bit parallel word on db11 to db0, where db11 is the msb and db0 is the lsb. 1 0 1 0 1 ad1 ad0 r/w a7 = 1 a6 = 1 a5 = 1 a4 = 1 a3 = 1 a2 = 1 a1 = 1 a0 = 1 st art cond by master address byte pointer byte most significant d at a byte channe l 0 dat a least significant d at a byte ack b y converter msb ack b y converter ack b y ad538x ack b y ad538x most significant d at a byte channe l 1 dat a least significant d at a byte ack b y converter ack b y converter most significant d at a byte channe l n dat a followed b y s top least significant d at a byte ack b y converter ack b y converter stop cond by master reg1 reg0 msb lsb msb lsb reg1 reg0 msb lsb msb lsb reg1 reg0 msb lsb msb lsb scl sda scl sda scl sda scl sda 03732-033 figure 33 . 2- byte, 1 2 c write operation
data sheet ad5381 rev. d | page 31 of 40 microprocessor inter facing parallel interface the ad5381 can be interfaced to a variety of 16 - bit microcon - trollers or dsp processors. figure 35 shows the ad5381 family interfaced to a generic 16 - bit microcontroller/dsp processor. the lower address lines from the processor are connected to a0 to a5 on the ad5381 . the upper address lines are decoded to provide a cs , ldac s ignal for the ad5381 . the fast interface timing of the ad5381 allows direct interface to a wide variety of microcontrollers and dsps, as shown in figure 35 . ad5381 to m c68hc11 the serial peripheral interface (spi) on the mc68hc11 is configured for m aster m ode (mstr = 1), c lock p olarity bit (cpol) = 0, and the c lock p hase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr) see the mc68hc11 user m anual. sck of th e mc 68hc11 drives the sclk of the ad5381 , the mosi output drives the serial data line (d in ) of the ad5381 , and the miso input is driven from d out . the sync signal is derived from a port line (pc7). when data is being transmitted to th e ad5381 , the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the mc 68hc11 is transmitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit c ycle. 03731-034 mc68hc11 ad5381 miso mosi sck pc7 sdo reset ser/par din sclk sync spi/i 2 c dvdd figure 34 . ad5381- to - mc68hc11 interface 03732-035 controller/ dsp processor 1 ad5381 address decode upper bits of address bus data bus a5 d15 d0 a4 a3 a2 a1 a0 r/w a5 a4 a3 a2 a1 a0 wr reg1 reg0 d11 d0 cs ldac 1 additional pins omitted for clarity. figure 35 . ad5381- to - parallel interface
ad5381 data sheet rev. d | page 32 of 40 ad5381 to pic16c6 x /7 x the pic16c6x/7x s ynchronous s erial p ort (ssp) is configured as an spi m aster with the clock polarity b it = 0. this is done by writing to the s ynchronous s erial p ort c ontrol r egister (sspcon). see the pic16/17 m icrocontroller u ser m anual. in this example i/o , p ort ra1 is being used to pulse sync and enable the serial port o f the ad5381 . this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations may be needed depending on the mode. figure 36 shows the connection diagram. 03732-036 pic16c6x/7x ad5381 sdi/rc4 sdo/rc5 sck/rc3 ra1 sdo reset ser/par din sclk sync spi/i 2 c dvdd figure 36 . ad5381- to - pic16c6 x /7 x interface ad5381 to 8051 the ad5381 requires a clock synchronized to the serial data. the 8051 serial interface must therefore be operated in mode 0. in this mode , serial data enters and exits through rxd , and a shift clock is output on txd. figure 37 shows how the 8051 is connected to the ad5381 . because the ad5381 shifts data out on the rising edge of the shift clock and latches data i n on the falling edge, the shift clock must be inverted. the ad5381 requires its data to be msb first. since the 8051 outputs the lsb first, the transmit routine must take this into account. 03732-037 8xc51 ad5381 rxd txd p1.1 sdo reset ser/par din sclk sync spi/i 2 c dvdd figure 37 . ad5381- to - 8051 interface ad 5381 to adsp - 2101/ adsp - 2103 figure 38 shows a serial interface between the ad5381 and the adsp - 2101/adsp - 2103. the adsp - 2101/adsp - 2103 should be set up to operate in sport t ransmit a lternate f raming m ode. the adsp -2 101/adsp - 2103 sport is programmed through the sport control register and configured as follows: i nternal c lock o pe ratio n, a ctive l ow f raming, and 16 -b it w ord l ength. transmission is initiated by writing a word to the tx register after the sport has been en abled. 03732-038 adsp-2101/ adsp-2103 ad5381 dr dt sck tfs rfs sdo reset ser/par din sclk dvdd spi/i 2 c sync figure 38 . ad5381- to - adsp - 2101/adsp -2 103 interface
data sheet ad5381 rev. d | page 33 of 40 application informat ion power supply decoupl ing in any circuit where accuracy is important, careful considera - t ion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5381 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5381 is in a system where multiple devices require an agnd - to - dgnd connection , t he connection should be made at one point only , a star ground point established as close to the device as possible . for supplies with multiple pins (av dd , dv dd ), th e se pins should be tied together. the ad5381 should ha ve ample supply bypassing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible and ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low e ffective s eries r esistance (esr) and e ffective s eries i nductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. the power su pply lines of the ad5381 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. a ground line routed between the d in and sclk lines will help reduce crosstalk between them ( this is not required on a multilayer board because there will be a separate ground plane, but separat - in g the lines will help). it is essential to minimize noise on the refout/refin line . avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough throu gh the board. a micro - strip technique is by far the best, but is not always possible with a double - sided board. in this tech - nique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. typical configuration circui t figure 39 shows a typical configuration for the ad5381 - 5 when configured for use with an external reference. in the circuit shown , all agnd, signal_gnd , and dac_gnd pins are tied together to a common agnd. agnd and dgnd are connected together at the ad5381 device. on power - up , the ad5381 defaults to external reference operation. all avd d lines are connected together and driven from the same 5 v source. it is recommended to d ecouple close to the device with a 0.1 f ceramic and a 10 f tantalum capacitor. in th is application , the reference for the ad5381 - 5 is provided externally from either an adr421 or adr431 2.5 v reference. suitable external reference s for the ad5381 - 3 include the adr280 1.2 v reference. the reference should be decoupled at the ref out /r ef in pin of the device with a 0.1 f capacitor. 03732-039 adr431/ adr421 ad5381-5 avdd dvdd signal_gnd dac_gnd dgnd vout39 vout0 agnd refout/refin refgnd 0.1f 10f 0.1f 0.1f avdd dvdd figure 39 . typical configuration with external reference figure 40 shows a typic al configuration when using the internal reference. on power - up , the ad5381 defaults to an external reference ; therefore, the internal reference needs to be config - ured a nd turned on via a w rite to the ad5381 control register . c ontrol r egister b it cr 10 all ows the user to choose the reference value ; b it cr 8 is used to select the internal reference. it is recommended to use the 2.5 v reference when avd d = 5 v, and the 1.25 v reference when avdd = 3 v. 03732-040 ad5381 avdd dvdd signal_gnd dac_gnd dgnd vout39 vout0 agnd refout/refin refgnd 0.1f 10f 0.1f 0.1f avdd dvdd figure 40 . typical configuration with internal reference digital connections have been omitted for clarity. the ad5381 contains an internal power - on reset circuit with a 10 ms brown - out time . if the power supply ramp rate exceeds 10 ms , the user should reset the ad5381 as part of the ini tialization process to ensure the calibration data i s loaded correctly in to the device.
ad5381 data sheet rev. d | page 34 of 40 monitor function the ad5381 channel monitor function consists of a multiplexer addressed via the interface , allowing any channel output to be routed to this pin for m onitoring using an external adc. in channel monitor mode , vout 39 becomes the mon_out pin, to which all monitored signals are routed. the channel monitor function must be enabled in the control regis ter before any channels are routed to mon_out. ta b le 17 contains the decoding information required to route any channel to mon_out. selecting c hannel a ddress 63 three - states mon_out. figure 41 shows a typical monitoring circuit impl emented using a 12 - bit sar adc in a 6 - lead sot - 23 package. the controller output port selects the channel to be monitored , and th e input port reads the converted data from the adc. ad7476 gnd sdata cs sclk vdd vin vout39/mon_out agnd din sync sclk dac_gnd signal_gnd vout0 vout38 avdd ad5381 output port input port controller 03732-041 figure 41 . typical channel monitoring circuit t oggle mode function the toggle mode function allows an output signal to be gener - ated using the ldac control signal that switches between two dac data registers. this function is configured using the sfr control register as follows. a write with reg1 = reg0 = 0 and a5 to a0 = 001100 specifies a control register write. the toggle mode function is enabled in groups of eight channels using b it cr 4 to bit cr 0 in the control register. see the ad5381 control register description. figure 42 shows a block diagram of toggle mode implementation. each of the 40 dac channels on the ad5381 contain an a and b data register. note that b registers can only be loaded when t oggle mode is enabled. the sequence of events when configurin g the ad5381 for toggle mode is 1. enable t oggle m ode for the required channels via the c ontrol r egister . 2. load d ata to the a registers . 3. load d ata to the b registers. 4. apply ldac . ldac is used to switch between the a and b registers in determining the analog output. the first ldac configures the output to reflect data in the a registers. this mode offers signif - i cant advantages if the user wants to generate a square wave at the output of all 40 channels , as might be req uired to drive a liquid crystal - based variable optical attenuator. in this case , the user writes to the control register and enables the toggle function by setting cr 4 to cr 2 = 0 , thus enabling the five gro ups of eight for toggle mode operation. the user must then load data to all 40 a and b registers. toggling ldac set s the output values to reflect the data in the a and b registers . t he frequency of the ldac det ermine s the frequency of the square wave output. toggle mode is disabled via the control register . t he first ldac following the disabling of the toggle mode will update the out - puts with the data contained in the a registers. thermal monitor function the ad5381 contains a temperature shutdown function to protect the chip i f multiple outputs are shorted. the short - circuit current of each output amplifier is typically 40 ma. operating the ad5381 at 5 v leads to a power dissipation of 20 0 mw per shorted amplifier. with five channels shorted, this leads to an extra watt of power dissipation. for the 100 - lead lqfp, the ja is typically 44c/w. the thermal monitor is enabled by the user via cr 6 in the control register. the output amplifiers on the ad5381 are automatically powered down if the die temperature exceeds approximately 130c. after a thermal shutdown has occurred, the user can re - enable the part by executing a soft power - up if the temperature has dropped below 130c or by turning of f the thermal monitor function via the control register.
data sheet ad5381 rev. d | page 35 of 40 12-bit dac dac register input data input register data register b data register a a/b vout ldac control input 03732-042 figure 42 . toggle mode function optical attenuators based on its high channel count, high resolution, monotonic behavior, and high level of integration, the ad5381 is i deally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (voa s ), and optical add - drop multiplexers (oadm s) . in these applications, each wavelength is individually extracted using an arrayed wave guid e; its power is monitored using a photodiode, transimped - ance amplifier and adc in a closed - loop control system. the ad5381 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexe d onto the fiber. this prevents information loss and saturation from occurring at amplification stages further along the fiber. utilizing fifo the ad5381 fifo mode optimizes total system update rates in applications where a large number of channels need t o be updated. fifo mode is only available when parallel interface mode is selected. the fifo en pin is used to enable the fifo. the status of fifo en is sampled during the initialization sequence. therefore, the fifo status can only be changed by resetting the device. in a telescope that provides for the cancel - lation of atmospheric distortion, for example, a large number of channels need to be updated in a short period of time. in such systems, as many as 400 channels need to be updated within 40 s . four - hundred channels require the use of 10 ad5381s. with fifo mode enabled, the data write cycle time is 40 ns; therefore , e ach group consisting of 40 channels can be fully loaded in 1.6 s. in fifo mode, a complete group of 40 chan - nels will update in 14.4 s. the time take n to update all 400 channels is 14.4 s + 9 1.6 s = 28.8 s. figure 44 shows the fifo operation scheme. attenuator attenuator attenuator attenuator awg awg fibre fibre dwdm out optical switch 11 12 1n?1 1n dwdm in ad5381, 40-channel, 12-bit dac n:1 multiplexer 16-bit adc controller tia/log amp (ad8304/ad8305) adg731 (40:1 mux) ad7671 (0v to 5v, 1msps) photodiodes add ports drop ports 03732-043 figure 43 . oadm u sing the ad5381 as p art of an optical attenuator
ad5381 data sheet rev. d | page 36 of 40 group a chnls 0?39 group b chnls 40?79 group c chnls 80?119 group d chnls 120?159 group e chnls 160?199 group f chnls 200?239 group g chnls 240?279 group h chnls 280?319 group i chnls 320?359 group j chnls 360?399 time to update 400 channels = 28.8 s 1.6s 14.4s 14.4s 1.6s fifo data load group a fifo data load group b output update time for group a 1.6s 14.4s fifo data load group j output update time for group j output update time for group b 03732-044 figure 44 . using fifo m ode 400 channels updated in u nder 30 s
data sheet ad5381 rev. d | page 37 of 40 outline dimensions compliant t o jedec s t andards ms-026-bed top view (pins down) 1 25 26 51 50 75 76 100 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 14.20 14.00 sq 13.80 16.20 16.00 sq 15.80 051706- a figure 45 . 100 - lead low profile quad flat package [lqfp] (st - 100 -1) dimensions shown in millimeters ordering gui de model 1 resolution temperature range avdd range output channels linearity error (lsb) package description package option ad5381bst z-3 12 bits C 40c to +85c 2.7 v to 3.6 v 40 1 100- lead lqfp st - 100 -1 ad5381bst z-3- reel 12 bits C 40c to +85c 2.7 v t o 3.6 v 40 1 100- lead lqfp st - 100 -1 ad5381bst z-5 12 bits C 40c to +85c 4.5 v to 5.5 v 40 1 100- lead lqfp st - 100 -1 ad5381bst z-5- reel 12 bits C 40c to +85c 4.5 v to 5.5 v 40 1 100- lead lqfp st - 100 -1 eval - ad538 0 eb z evaluation kit 1 z = rohs compliant part .
ad5381 data sheet rev. d | page 38 of 40 notes
data sheet ad5381 rev. d | page 39 of 40 note s
ad5381 data sheet rev. d | page 40 of 40 notes i 2 c refers to a communications protocol originally develope d by philips semiconductors (now nxp semiconductors). ? 200 4C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d0373 2-0- 9 /12(d )

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